Jim Lewis

Jim Lewis has extensive experience in VHDL design, verification, and training, currently serving as the Director of VHDL Training at SynthWorks since January 1997, where responsibilities include overseeing engineering and marketing efforts in FPGA design. As Chief Architect of Open Source VHDL Verification Methodology (OSVVM) since January 2012, Jim develops a leading VHDL verification methodology with a robust utility library. Additionally, Jim chairs the VHDL Standards Working Group, contributing to the VHDL-2019 standards effort. Previous roles include consulting for various companies on VHDL ASIC and FPGA design, along with engineering positions at notable firms such as TRW and Zycad. Jim's academic background includes a Master of Science in Electrical Engineering from Purdue University.