Ryan T.

Ryan T. is a seasoned engineer with extensive experience in RTL design and verification, currently serving as a Senior Design Engineer at Tarana Wireless, Inc. since January 2014, focusing on NLOS wireless PHY datapath and baseband packet processing. Prior to that, Ryan T. held the position of Senior FPGA Engineer at zonare medical systems from November 2000 to December 2013, where responsibilities included RTL design and verification for ultrasound systems, encompassing serdes data acquisition, bus interfaces, and signal processing blocks. Ryan T. holds a Master's degree in Electrical Engineering from San Jose State University and a Bachelor's degree in Computer Engineering from the University of Illinois Urbana-Champaign.