Amit Kulkarni

Amit Kulkarni, PhD, SMIEEE, currently serves as a Senior Design Verification Engineer at u-blox, focusing on ASIC verification and block-level digital verification using UVM, alongside developing VIP for address space functional coverage. Amit is also an IEEE Senior Member and has previously held roles as a Senior FPGA Engineer and Embedded Software Engineer at duagon AG, where responsibilities included RTL code generation and FPGA IP verification. With a solid academic foundation, Amit completed a PhD in Electrical Engineering at Ghent University, where research involved dynamic circuit specialization on FPGAs, and has contributed to various projects across multiple organizations, including Ericsson, ETH Zurich, and Volvo Car Corporation.