Syed Danish Kamal

Syed Danish Kamal has a diverse work experience in the field of ASIC physical design engineering, modeling and methodology engineering, and systems engineering.

From 2014 to 2017, they worked at Infosys Limited as a Systems Engineer, focusing on physical design engineering. During this time, they handled projects related to a 14nm program for mobile and wireless communication. Syed Danish took ownership of block execution and worked on various sub-blocks of medium complexity and a super-block.

In 2017, Syed joined ARM as a Design Engineer, specifically in modeling and methodology engineering. Syed Danish 'smain role involved validating front-end models/views of the design.

From 2018 to 2021, they worked at Synopsys Inc as an ASIC physical design engineer. Syed Danish held the position of Sr-I and later Sr-II. Syed Danish 'sresponsibilities included physical design engineering for ASICs.

In 2022, Syed took on the role of Senior Technical Lead at SeviTech Systems Pvt. Ltd. This position allowed him to further enhance their technical expertise.

Currently, they are employed at Veriest as an ASIC Backend Engineer, starting in 2022.

Overall, Syed Danish Kamal's work experience demonstrates their proficiency in ASIC physical design engineering, modeling and methodology engineering, and systems engineering roles.

Syed Danish Kamal completed their Master's degree (MTech) in Microelectronics from the Indian Institute Of Information Technology Allahabad from 2012 to 2014. Prior to that, from 2007 to 2011, they obtained a Bachelor's degree (BTech) in Electronics and Communications Engineering from Integral University, Lucknow. In their earlier education, Syed Danish Kamal attended Kendriya Vidyalaya, where they completed their Intermediate in PCMB (Physics, Chemistry, Mathematics, and Biology) in 2007 and their High School in Science in 2005.