Shobhit Agrawal

Shobhit Agrawal is a highly experienced engineer specializing in micro-architecture design and implementation for digital signal processing (DSP) systems. Currently serving as a Sr. Principal Design Engineer at Cadence Design Systems since November 2016, Shobhit is responsible for optimizing various Tensilica® DSP cores targeted at applications in the Internet of Things, deep neural networks, and wearables. Prior experience includes a role as a Digital Design Engineer at Analog Devices, where Shobhit contributed to the design of DSP algorithms and held a patent for innovative work on a blocker detector. Academic involvement includes grading and mentoring roles at the University of Southern California, coupled with a graduate engineer trainee position at Samtel Avionics and Defense Systems. Shobhit's educational background includes a Master of Science in Electrical Engineering from the University of Southern California and a Bachelor's degree in Electronics and Communication from Maulana Azad National Institute of Technology.