Paul Yip

Paul Yip is a Senior Physical Design Engineer at Sintegra Inc. since April 2017, where responsibilities include designing a cluster utilizing TSMC-7nm, managing over 3 million cells, 80+ macros, and implementing a semif-custom clock tree using Innovus, Tempus, and Genus. Prior to this role, Paul Yip served as a Sr Staff Engineer and Manager at Sun Microsystems from 1997 to March 2017. Paul Yip holds both a Master of Science in Electrical Engineering and a Bachelor of Science in Electrical Engineering with honors from the University of Illinois Urbana-Champaign.